Semiconductor device and manufacturing method thereof

ABSTRACT

To provide a method for manufacturing a semiconductor device, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant with causing neither via-connection failure nor short-circuit failure even when lower level interconnect is covered with etching stopper. The method comprises the processes of forming a layered film with a silicon oxide film on upper layer of a methylsiloxane type film and forming the layered film using a hard mask. When the etching stopper is etched, the silicon oxide film acts as a hard mask for the methylsiloxane type film, and transfer of faceting to the methylsiloxane type film is prevented. Thus, parasitic capacitance of multi-level interconnect can be reduced without causing via-connection failure and short failure.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device providedwith multi-level interconnects and a manufacturing method thereof.

[0003] In particular, the invention relates to a semiconductorintegrated circuit device having multi-level interconnects with lowparasitic capacitance and operated at high speed of several hundreds ofMHz or more and a manufacturing method thereof.

[0004] 2. Description of Related Art

[0005] In a semiconductor integrated circuit device operated at highspeed of several hundreds of MHz or more, signal propagation delay dueto parasitic capacitance in multi-level interconnects is significant.

[0006]FIG. 1 is a schematical plan view of multi-level interconnects.Reference numeral 1 denotes a semiconductor substrate, 4 a lower levelinterconnect, 14 a via, and 24 a higher level interconnect. Normally,adjacent level interconnects are laid out in directions crossingperpendicularly to each other. This means that the area to face eachother is small between higher level and lower level interconnects. As aresult, parasitic capacitance between adjacent interconnects in a levelis generally larger than that between interconnects in different levels,and exert more influence on signal propagation delay. Accordingly,attempts have been made to reduce parasitic capacitance between theadjacent interconnects in a level by replacing the insulating filmmaterial (silicon oxide film (specific dielectric constant: k˜4) andsilicon nitride film (k˜7)) between adjacent interconnects in a levelwith insulating film material with lower dielectric constant.

[0007] Methylsiloxane type film is one of the low dielectric constantfilm (k˜about 3 or lower). This is a film having Si—CH₃ bond and Si—O—Sibond as main components. In addition, Si—H bond or Si—C—Si bond may becontained. There are the following methods to form the film:spin-coating and chemical vapor deposition (CVD). In the spin-coating,oligomer solution containing methylsiloxane (spin-on glass (SOG)) isdeposited by spin-coating, and then is cured. In the CVD, a gascontaining Si—CH₃ bond reacts with oxidizing gas in a CVD chamber. Theadvantageous feature of methylsiloxane type film is that it has highheat-resistant property and is stable in heat treatment (up to 450° C.)in the manufacturing process of multi-level interconnects.

[0008] However, when high-pressure oxygen plasma treatment is performedon methysiloxane type film, the film is deteriorated due to oxygenradicals in the plasma and absorbs moisture, and the quality of the filmsuch as electrical characteristics is deteriorated. For this reason,conventional type patterning method cannot be used, in which a resistmask is removed by high-pressure oxygen plasma treatment aftertransferring the pattern.

[0009] A first method to solve this problem is disclosed in JapanesePatent Application 151102/1988, which describes the use of low-pressureoxygen plasma to remove the resist. According to this method,deterioration of the quality of methylsiloxane type film is suppressed.This is because oxygen ions in the low-pressure oxygen plasma modify thesurface of the methylsiloxane type film to fine silicon oxide, and thissurface layer protects inner part of the film from oxygen radicals.

[0010] There is a second method to prevent deterioration of the qualitywhen the resist is removed, and this is disclosed in JP-A-87502/1999. Itis a method to transfer resist pattern to hard mask, and after removingthe resist in advance, the methylsiloxane type film is etched using thehard mask.

[0011]FIG. 2 to FIG. 4 each represents a cross-sectional view showing ofa manufacturing process to explain the second method. On amethylsiloxane type film 6, a hard mask material 8 such as siliconnitride is deposited. A silicon oxide film 27, and further, a resist 9are formed on it, and the resist is patterned by lithography (FIG. 2).After etching the silicon oxide film 27 using the resist mask 9, theresist 9 is removed (FIG. 3). In this case, the methylsiloxane type film6 is covered with the hard mask material 8, and it is not exposed tooxygen plasma, and hence, it is not deteriorated. After transferring thepattern to the hard mask 8, the silicon oxide film 27 is removed. Then,using the hard mask 8, the methylsiloxane type film 6 is patterned (FIG.4).

[0012] According to the first method as described above, it is notpossible to form a hole pattern or a trench pattern with high aspectratio (depth over diameter or depth over trench width). When the aspectratio increases, the number of ions impinging on the pattern side-wallsurface is decreased. As a result, surface passivation layer is notformed on the methylsiloxane type film and its quality is deteriorated.In practical application, this method is effective only in the casewhere the aspect ratio <3.

[0013] When the methylsiloxane type film is fabricated by the secondmethod as described above, shoulder portion of the hard mask 8 collapsesdiagonally as shown in FIG. 4 (faceting). In case low resistance copperwire is used as the lower level interconnect 4, an etching stopper 5 onthe surface of the interconnect must be etched (FIG. 5). As the etchingstopper 5, silicon nitride film, silicon carbide film, etc. are used.Under the etching condition to etch the etching stopper 5, both the hardmask 8 and the methylsiloxane type film 6 are etched at the similar rateas the etching stopper 5. As a result, faceting of the hard mask 8occurs more remarkably (FIG. 6). When there is a portion where the hardmask 8 completely disappears, faceting occurs on the methylsiloxane typefilm 6 underneath. Further, the faceting is expanded in argonsputter-etching, which is performed as pre-treatment (cleaning) of thenext metal deposition (FIG. 7).

[0014] The first problem caused by the faceting is that sputtereddielectrics 98 are deposited on pattern bottom in case of argonsputter-etching, and this results in via-connection failure. Thefaceting prior to the sputter-etching increases the amount of thesputtered dielectrics, so increases the via-connection failure.

[0015] The second problem caused by the faceting is that buried metals14 in the pattern are not completely separated from each other, and thiscauses short-circuit failure (FIG. 8).

SUMMARY OF THE INVENTION

[0016] It is an object of the present invention to provide asemiconductor device and a manufacturing method thereof, by which it ispossible to form a trench or a hole with high aspect ratio on amethylsiloxane type film with low dielectric constant without causingvia-connection failure and short circuit failure due to faceting evenwhen lower level interconnects are covered with etching stopper.

[0017] According to an aspect of the method for manufacturing asemiconductor device of the present invention, inter-level dielectricsfor forming holes for vias or trenches for interconnects are fabricatedas layered films of a methylsiloxane type film and a differentinsulating film formed on the film, and the layered films are processedusing a hard mask. As a result, hole pattern or trench pattern istransferred to the hard mask using a resist, and the resist is thenremoved. In this case, deterioration of the quality of themethylsiloxane type film can be prevented because the methylsiloxanetype film is covered with the insulating film.

[0018] Also, when a hole or a trench is formed on the layered films, itis possible to prevent transfer of the faceting of the hard mask to themethylsiloxane type film because the insulating film is formed betweenthe methylsiloxane type film and the hard mask. Thus, the first and thesecond problems as described above can be overcome. By setting theetching rate of the insulating film to ⅓ or less of that of the hardmask, the insulating film acts as a hard mask for the methylsiloxanetype film, and the higher effects can be obtained. As an example of thematerial for the insulating film, it is effective to use silicon oxidefilm because it can suppress the increase of parasitic capacitancebetween the interconnects.

[0019] Further, in case the dual damascene process in which holes forvias or trenches for interconnects are formed at the same time, layeredfilms of methylsiloxane type film, a different insulating film and ahard mask are deposited on the similar layered films, and then the holeand the trench are formed at the same time. In this case, the insulatingfilm prevents quality deterioration caused by removal of the resist onthe methylsiloxane type film under the insulating film, and also thetransfer of the faceting of the hard mask to the methylsiloxane typefilm can be prevented. In case of the dual damascene process in whichtrench pattern is transferred to the higher level hard mask and holepattern is transferred to the lower level hard mask, the resist used forpatterning of the lower level hard mask is removed by low-pressureoxygen plasma treatment, and quality deterioration of the methylsiloxanetype film formed on the lower level hard mask can be suppressed.

[0020] In case the etching stopper is formed on the lowermost layer ofthe inter-level dielectrics, the hard mask on the exposed portion isremoved at the same time when the hole is formed on the etching stopper.As a result, it is possible to reduce parasitic capacitance between themulti-level interconnects.

[0021] According to an aspect of a semiconductor device of the presentinvention, inter-level dielectrics with dual damascene interconnectsformed on it are made as layered films comprising a first methylsiloxanetype film, a first insulating film, a hard mask, a second methylsiloxanetype film, and a second insulating film in this order from below, andthe manufacturing method as described above can be applied. The decreaseof production yield caused by via-connection failure or short-circuitfailure of multi-level interconnects can be prevented, and asemiconductor integrated circuit device to be operated at high speed ofseveral hundreds of MHz or more can be manufactured at lower cost.

[0022] Other and further objects, features and advantages of theinvention will appear more fully from the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] A preferred form of the present invention illustrated in theaccompanying drawings in which:

[0024]FIG. 1 is a schematical plan view of conventional type multi-levelinterconnects;

[0025]FIG. 2 is a cross-sectional view showing a process formanufacturing conventional type multi-level interconnects;

[0026]FIG. 3 is a cross-sectional view showing a process formanufacturing conventional type multi-level interconnects;

[0027]FIG. 4 is a cross-sectional view showing a process formanufacturing conventional type multi-level interconnects;

[0028]FIG. 5 is a cross-sectional view showing a manufacturing processto explain problems in the conventional example;

[0029]FIG. 6 is a cross-sectional view showing a manufacturing processto explain problems in the conventional example;

[0030]FIG. 7 is a cross-sectional view showing a manufacturing processto explain problems in the conventional example;

[0031]FIG. 8 is a cross-sectional view showing a manufacturing processto explain problems in the conventional example;

[0032]FIG. 9 is a cross-sectional view of a manufacturing process of afirst embodiment of the present invention;

[0033]FIG. 10 is a cross-sectional view of a manufacturing process of afirst embodiment of the present invention;

[0034]FIG. 11 is a cross-sectional view of a manufacturing process of afirst embodiment of the present invention;

[0035]FIG. 12 is a cross-sectional view of a manufacturing process of afirst embodiment of the present invention;

[0036]FIG. 13 is a cross-sectional view of a manufacturing process of afirst embodiment of the present invention;

[0037]FIG. 14 is a plan view showing a process for manufacturing thefirst embodiment of the present invention;

[0038]FIG. 15 is a cross-sectional view of a process for manufacturingthe first embodiment of the present invention;

[0039]FIG. 16 is a cross-sectional view of a process for manufacturingthe first embodiment of the present invention;

[0040]FIG. 17 is a cross-sectional view of a process for manufacturingthe first embodiment of the present invention;

[0041]FIG. 18 is a plan view of a process for manufacturing the firstembodiment of the present invention;

[0042]FIG. 19 is a cross-sectional view of a process for manufacturingthe first embodiment of the present invention;

[0043]FIG. 20 is a plan view of a process for manufacturing the firstembodiment of the present invention;

[0044]FIG. 21 is a diagram showing relationship between sputter-etchedthickness before deposition of vias and interconnects and via-connectionyield of vias;

[0045]FIG. 22 is a cross-sectional view of a process for manufacturing asecond embodiment of the present invention;

[0046]FIG. 23 is a cross-sectional view of a process for manufacturingthe second embodiment of the present invention;

[0047]FIG. 24 is a cross-sectional view of a process for manufacturingthe second embodiment of the present invention;

[0048]FIG. 25 is a cross-sectional view of a process for manufacturingthe second embodiment of the present invention;

[0049]FIG. 26 is a cross-sectional view of a process for manufacturingthe second embodiment of the present invention;

[0050]FIG. 27 is a cross-sectional view of a process for manufacturingthe second embodiment of the present invention;

[0051]FIG. 28 is a cross-sectional view of a process for manufacturing athird embodiment of the present invention;

[0052]FIG. 29 is a cross-sectional view of a process for manufacturingthe third embodiment of the present invention;

[0053]FIG. 30 is a plan view of a process for manufacturing the thirdembodiment of the present invention;

[0054]FIG. 31 is a cross-sectional view of a process for manufacturingthe third embodiment of the present invention;

[0055]FIG. 32 is a plan view of a process for manufacturing the thirdembodiment of the present invention;

[0056]FIG. 33 is a cross-sectional view of a process for manufacturingthe third embodiment of the present invention;

[0057]FIG. 34 is a cross-sectional view of a process for manufacturingthe third embodiment of the present invention;

[0058]FIG. 35 is a cross-sectional view of a process for manufacturingthe third embodiment of the present invention; and

[0059]FIG. 36 is a cross-sectional view of a process for manufacturingthe third embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT EXAMPLE 1

[0060]FIG. 9 to FIG. 20 each represents a cross-sectional view or a planview of a process for manufacturing a first embodiment of asemiconductor device of the present invention, in which single damasceneprocess is applied for forming multi-level interconnects.

[0061] As shown in FIG. 9, a first inter-level dielectric film 2 isformed on a silicon substrate 1 where a device component is fabricated.Then, a contact hole is opened, and titanium nitride is buried by CVDmethod. By chemical-mechanical polishing, the metal outside the hole isremoved, and a contact plug 3 is formed. In the figure, a MOS transistoris shown as a device component.

[0062] Next, as shown in FIG. 10, a second inter-layer dielectric 12 isformed, and a trench for a first level interconnect is fabricated.Sputter-etching is performed for the time as long as a 20-nm-thickblanket silicon oxide film is removed. Titanium nitride and copper arethinly formed by sputtering. Further, copper plating is performed tobury the trench with layered films of a barrier metal film 4 acomprising titanium nitride and a copper film 4 b. Further, bychemical-mechanical polishing, titanium nitride and copper outside thetrench were removed, and first-level interconnects 4 a and 4 b wereformed. A plan view of the process in this stage is shown in FIG. 11.Here, FIG. 10 is a cross-sectional view along the line A-B in FIG. 11.The relationship between this cross-sectional view and the top view isthe same in the description given below.

[0063] Next, as shown in FIG. 12, a silicon nitride film was formed inthickness of 50 nm by plasma CVD method as an etching stopper 5 of thefirst level interconnect. Then, 300-nm-thick organic SOG film was coatedas a methylsiloxane type film 6, and this was cured in nitrogen ambientat 425° C. Further, by plasma CVD method, a silicon oxide film 7 wasformed in thickness of 100 nm, and a silicon nitride film 8 was formedin thickness of 100 nm as a hard mask 8.

[0064] Next, as shown in FIG. 13, reactive ion etching was performedusing a resist 9 as mask, and via pattern was transferred from theresist 9 to the hard mask 8. In this etching process, it is necessary tostop the etching at the silicon oxide film 7 without exposing the lowerlevel organic SOG film as shown in the plan view of FIG. 14. There is noneed to stop the etching exactly at the upper surface of the siliconoxide film 7 as shown in FIG. 13, and there is no problem even when thesilicon oxide film is etched to some extent.

[0065] Then, as shown in FIG. 15, the resist 9 was removed by ICP typeasher, and reactive ion etching was performed using the silicon nitridefilm 8 as hard mask, and etching was performed on the silicon oxide film7 and the organic SOG film 6. In this etching process, etchingselectivity or selection ratio of the silicon oxide and the organic SOGfilm to the silicon nitride was 10. By this etching process, filmthickness of the hard mask was turned to 60 nm.

[0066] Next, as shown in FIG. 16, the space inside the hole was cleanedusing wet solution, and the etching stopper 5 was removed by etching,and upper surface of the first level interconnects 4 a and 4 b wereexposed. In this case, almost the entire hard mask on upper portion ofthe pattern disappeared. When the upper surfaces of the first levelinterconnects 4 a and 4 b were exposed, the hard mask 8 may remain.However, it is preferable to remove it in the etching process byover-etching in order to reduce parasitic capacitance betweeninterconnects.

[0067] Further, as shown in FIG. 17, sputter-etching was performed forthe time as long as a 20-nm-thick blanket silicon oxide film is removed,and titanium nitride and copper were thinly formed by sputtering. Then,by copper plating, layered films of the barrier metal film 4 acomprising titanium nitride and the copper film 4 b was buried in thehole. Further, by chemical-mechanical polishing, titanium nitride andcopper were removed, and vias 14 a and 14 b were formed. A plan view ofthe process in this stage is shown in FIG. 18.

[0068] Then, as shown in FIG. 19, the procedure of FIG. 12 to FIG. 18was repeated, and second level interconnects 24 a and 24 b were formed.Reference numeral 15 denotes a silicon nitride film as an etchingstopper, 16 is an organic SOG film as methylsiloxane type film, 17 asilicon oxide film, 24 a titanium nitride used as barrier metal film,and 24 b a copper layer. A plan view of the process in this stage isshown in FIG. 20. This process is different from the process shown inFIG. 12 to FIG. 18 in that film thickness of the organic SOG film 16 isas thin as 200 nm and that hole pattern of vias is changed to trenchpattern of the second level interconnects.

[0069] In the semiconductor device of Example 1 as formed above, yieldof the multilevel interconnects was evaluated. As a result, viaconnection yield of 0.25 μm diameter vias and insulation yield of 0.25μm spacing interconnects were both 95% or more, and no decrease of yielddue to faceting was observed.

[0070] Further, the process from FIG. 12 to FIG. 20 of Example 1 wasrepeated, and 3-level interconnects were formed, and capacitance betweenadjacent wires of the second level interconnects was measured. Effectivedielectric constant between the adjacent wires thus obtained was 3.3.

[0071] In the above Example, silicon nitride film was used as hard mask,but this may contain Si—H bond in addition to the main component. Also,the film may replace silicon carbide film or may contain Si—H bond orSi—CH₃ bond in addition to the main component of silicon carbide film.

[0072] In the above Example, the organic SOG film was used asmethylsiloxane film, while Si—H bond or Si—C—Si bond may be contained inaddition to the main components of Si—CH₃ bond and Si—O—Si bond. Also,the film may be formed by CVD method instead of coating method. Or,oligomer solution mixed with organic polymer may be coated in advance,and organic polymer may be decomposed and removed by curing, and lowdensity organic SOG thus prepared may be used.

[0073] The materials of the hard mask and methylsiloxane film are thesame in the examples as described below.

[0074] The effect of sputter-etching length is shown in FIG. 21. Here,the samples were the same as that shown above except for the length ofsputter-etching. The sputter-etching length is represented by thesputter-etched thickness, which is the decrease in thickness when thesputter-etching for the same length is applied to a blanketsilicon-oxide film.

EXAMPLE 2

[0075]FIG. 22 to FIG. 27 each represents a cross-sectional view or aplan view of a manufacturing process of a semiconductor device inExample 2 of the present invention where dual damascene process isapplied for formation of multi-level interconnects. In this Example, theprocess from FIG. 9 to FIG. 14 is the same as in Example 1.

[0076] After the process of FIG. 13, the resist 9 was removed as shownin FIG. 22. A second organic SOG film was coated as a methylsiloxanefilm 16 in thickness of 200 nm, and this was cured under nitrogenambient at 425° C. Further, a second silicon oxide film 17 was formed inthickness of 100 nm by plasma CVD method, and a silicon nitride film wasformed in thickness of 150 nm as a second hard mask 18.

[0077] Next, as shown in FIG. 23, reactive ion etching was performedusing a second resist 19 as mask, and the second level interconnectpattern was transferred to the second hard mask 18. In this etchingprocess, it is necessary to stop the etching in the second silicon oxidefilm 17 without exposing lower level second organic SOG film 16 as shownin the plan view of FIG. 24. There is no need to stop the etchingexactly on the upper surface of the second silicon oxide film 17 asshown in FIG. 23. The second silicon oxide film may be etched if thesecond organic SOG film 16 is not exposed.

[0078] Next, as shown in FIG. 25, the resist 19 was removed by ICP typeasher, and reactive ion etching was performed using the second siliconnitride film 18 and the first silicon nitride film 8 as hard masks, andetching was performed on the first silicon oxide film 7 and the secondsilicon oxide film 17 as well as the first organic SOG film 6 and thesecond organic SOG film 16. In this etching process, etching selectivityof the silicon oxide and the organic SOG to silicon nitride was 10. Bythis etching process, film thickness of the exposed portion of each ofthe first hard mask 8 and the second hard mask 18 was turned to 60 nm.As a result, via holes were formed in the layered film of the firstorganic SOG film 6 and the first silicon oxide film 7. Also, a trenchfor the second level interconnect was formed in the layered film of thesecond organic SOG film 16 and the second silicon oxide film 17.

[0079] Next, as shown in FIG. 26, the spaces in the hole and the trenchwere cleaned using wet solution, and etching was performed on theetching stopper 5. In this case, exposed portions of the first hard mask8 and the second hard mask 18 almost completely disappeared. The hardmasks 8 and 18 on the exposed portions may remain after the etchingstopper 5 on the upper surface of the first level interconnects 4 a and4 b is completely removed. However, it is preferable to completelyremove them by over-etching because parasitic capacitance betweeninterconnects can be reduced.

[0080] Further, as shown in FIG. 27, sputter-etching was performed for20 nm as measured using blanket silicon oxide film, and titanium nitrideand copper were thinly formed by sputtering. Then, by copper plating,layered films of a barrier metal film 34 a comprising titanium nitrideand a copper film 34 b were buried in the hole and the trench. Further,by chemical-mechanical polishing, titanium nitride and copper outsidethe hole and the trench were removed. Consequently, vias 34 a and 34 b,and interconnects 34 a and 34 b were fabricated in the layered films.

[0081] On the multi-level interconnects of the Example 2 thus prepared,the yield was evaluated. As a result, via connection yield of 0.25 μmdiameter vias and insulation yield of 0.25 μm spacing interconnects wereboth 95% or more, and no decrease of yield due to faceting was observed.

[0082] Further, by repeating the process from FIG. 12 to FIG. 14 ofExample 1 and the process from FIG. 22 to FIG. 27 of Example 2, 3-levelinterconnects were formed, and capacitance between adjacentinterconnects of the second level interconnects was measured. Effectivedielectric constant of the adjacent wires thus obtained was 3.6. Theincrease of effective dielectric constant compared with Example 1 isattributed to the fact that the silicon nitride film 8 for the firsthard mask of 100 nm in thickness remains in the inter-level dielectrics.

EXAMPLE 3

[0083]FIG. 28 to FIG. 36 each represents a cross-sectional view or aplan view of a manufacturing process of a semiconductor device inExample 3 of the present invention where dual damascene process isapplied for formation of multi-level interconnects. In this example, theprocesses from FIG. 9 to FIG. 12 are the same as in Example 1.

[0084] After the process of FIG. 12, as shown in FIG. 28, a secondorganic SOG film 16 was coated in thickness of 200 nm as amethylsiloxane film 16, and this was cured in nitrogen ambient at 425°C. Further, by plasma CVD method, a second silicon oxide film 17 wasformed in thickness of 100 nm, and a silicon nitride film was formed inthickness of 100 nm as a second hard mask 18.

[0085] Next, as shown in FIG. 29, reactive ion etching was performedusing a first resist 19 as mask, and the pattern of the second levelinterconnects was transferred to the second hard mask 18. In thisetching process, it is necessary to stop the etching in the secondsilicon oxide film 17 without exposing the second organic SOG film 16 asshown in the plan view of FIG. 30. There is no need to stop the etchingexactly on the upper surface of the second silicon oxide film 17 asshown in FIG. 29. The second silicon oxide film 17 may be removed tosome extent if the second organic SOG film 16 is not exposed.

[0086] Next, as shown in FIG. 31, the first resist 19 was removed by ICPtype asher, and the second resist 9 was formed and patterned usinglithography. Then, via hole pattern was transferred to the secondsilicon oxide film 17 and the second organic SOG film 16. In thisetching process, it is necessary to etch the first hard mask completely.There is no need to stop the etching exactly on the upper surface of thefirst silicon oxide film 7 in FIG. 31, and the first silicon oxide film7 and the first organic SOG film 6 may be etched to some extent.

[0087] Next, as shown in FIG. 33, low-pressure reactive ion etching wasperformed using oxygen at the pressure of 10 mTorr, and the secondresist 9 was removed. Under this condition, aspect ratio of the holeformed in the second organic SOG film 16 and the second silicon oxidefilm 17 was 3 or less in a hole pattern of 0.25 μm in diameter. Byremoving the second resist 9 at low pressure, the quality deteriorationdid not occur in the second organic SOG film 16.

[0088] Further, as shown in FIG. 34, reactive ion etching was performedusing the second silicon nitride film 18 and the first silicon nitridefilm 8 as hard mask, and etching was performed on the first siliconoxide film 7 and the second silicon oxide film 17 as well as the firstorganic SOG film 6 and the second organic SOG film 16. In this etchingprocess, etching selectivity of the silicon oxide film and the organicSOG to silicon nitride was 10. By this etching process, film thicknessof the exposed portions of the first hard mask 8 and the second hardmask 18 was turned to 60 nm. As a result, via-holes were formed in thelayered films of the first organic SOG film 6 and the first siliconoxide film 7. Also, trench was formed in the layered films of the secondorganic SOG film 16 and the second silicon oxide film 17.

[0089] Next, as shown in FIG. 35, the surface of the holes and thetrenches were cleaned using wet solution, and etching was performed onthe etching stopper 5. In this case, exposed portions of the first hardmask 8 and the second hard mask 18 disappeared almost completely. Ifupper surfaces of the first level interconnects 4 a and 4 b are exposed,there is no problem even when the hard masks 8 and 18 of the exposedportions may remain. However, if it is completely removed, it ispossible to reduce parasitic capacitance between the interconnects.

[0090] Further, as shown in FIG. 36, sputter-etching was performed forthe time as long as a 20-nm-thick blanket silicon oxide film is removed,and titanium nitride and copper were formed thinly by sputtering. Then,by copper plating, layered films of a barrier metal film 34 a comprisingtitanium nitride and a copper film 34 b were buried in the hole and thetrench. Further, by chemical-mechanical polishing, titanium nitrideoutside the hole and the trench were removed. Consequently, vias 34 aand 34 b, and interconnects 34 a and 34 b were fabricated in the layeredfilms.

[0091] On the multi-level interconnects of Example 3 thus prepared, theyield was evaluated. As a result, via connection yield of 0.25 μmdiameter vias and insulation yield of 0.25 μm spacing interconnects wereboth 95% or more, and no decrease of yield due to faceting was observed.

[0092] In the above examples, description has been given on the casewhere titanium nitride was used as barrier metal film, while theinvention is not limited to these examples, and film of nitride ofrefractory metal such as tantalum nitride, tungsten nitride, etc. may beused.

[0093] According to the present invention, it is possible to preventvia-connection failure and short failure in multi-level interconnects.

[0094] The foregoing invention has been described in terms of preferredembodiments. However, those skilled, in the art will recognize that manyvariations of such embodiments exist. Such variations are intended to bewithin the scope of the present invention and the appended claims.

What is claimed is:
 1. A method for manufacturing a semiconductordevice, comprising: a first process for forming a methylsiloxane typefilm on or over a first conductor film; a second process for forming aninsulating film different from the methylsiloxane type film on themethylsiloxane type film; a third process for forming a hard mask on theinsulating film; a fourth film for transferring a pattern on the hardmask using a resist as mask, and removing the resist; a fifth processfor partially removing layered films of the methylsiloxane type film andthe insulating film using the hard mask as mask, and for exposing a partof said first conductor film; and a sixth process for forming a secondconductor film electrically connected with said first conductor film ona recess of said layered films formed in said fifth process.
 2. A methodfor manufacturing a semiconductor device according to claim 1, whereinetching rate of said insulating film is ⅓ or less of etching rate of thehard mask.
 3. A method for manufacturing a semiconductor deviceaccording to claim 2, wherein said insulating film is a silicon oxidefilm.
 4. A method for manufacturing a semiconductor device according toclaim 3, wherein said methylsiloxane type film is an organic SOG film.5. A method for manufacturing a semiconductor device according to claim4, wherein said hard mask is a silicon nitride film or a silicon carbidefilm.
 6. A method for manufacturing a semiconductor device according toclaim 5, wherein said method comprises a process for forming an etchingstopper on said first conductor film prior to said first process, saidmethylsiloxane type film is formed on said etching stopper in the firstprocess, and the layered films of said etching stopper, saidmethylsiloxane film and said insulating film are partially removed inthe fifth process.
 7. A method for manufacturing a semiconductor deviceaccording to claim 6, wherein said etching stopper is a silicon nitridefilm or a silicon carbide film.
 8. A method for manufacturing asemiconductor device according to claim 7, wherein said hard mask isalso removed in said fifth process.
 9. A system for manufacturing asemiconductor device as described in claim 5, wherein said first andsaid second conductor films are layered films of a barrier metal filmand a copper film.
 10. A method for manufacturing a semiconductor deviceaccording to claim 9, wherein said barrier metal film is a titaniumnitride film or a tantalum nitride film.
 11. A method for manufacturinga semiconductor device according to claim 5, wherein said firstconductor film is a via, and said second conductor film is aninterconnect.
 12. A method for manufacturing a semiconductor deviceaccording to claim 5, wherein said first conductor film is aninterconnect, and said second conductor film is a via.
 13. A method formanufacturing a semiconductor device, comprising: a first process forforming a first methylsiloxane type film on or over a firstinterconnect; a second process for forming a first insulating filmdifferent from the methylsiloxane type film on said first methylsiloxanetype film; a third process for forming a first hard mask on said firstinsulating film; a fourth process for transferring a hole pattern ofsaid first hard mask using a first resist as mask, and removing saidfirst resist; a fifth process for forming a second methylsiloxane typefilm on said first hard mask; a sixth process for forming a secondinsulating film different from the methylsiloxane type film on saidsecond methylsiloxane type film; a seventh process for forming a secondhard mask on said second insulating film; an eighth process fortransferring a trench pattern having in-plane overlapping with said holepattern on said second hard mask using a second resist as mask, andremoving said second resist; a ninth process for forming a trench inlayered films of said second methylsiloxane type film and said secondinsulating film using said first and said second hard masks as masks,and forming a hole in layered films of said first methylsiloxane typefilm and said first insulating film, and exposing a part of said firstinterconnect; and a tenth process for forming a conductor filmelectrically connected with said first interconnect inside said trenchand said hole formed in said ninth process.
 14. A method formanufacturing a semiconductor device according to claim 13, wherein saidfirst and said second insulating films have etching rate of ⅓ or less ofthat of said first and said second hard masks.
 15. A method formanufacturing a semiconductor device according to claim 14, wherein saidfirst and said second insulating films are silicon oxide films.
 16. Amethod for manufacturing a semiconductor device according to claim 15,wherein said first and said second methylsiloxane type films are organicSOG films.
 17. A semiconductor device according to claim 16, whereinsaid first and said second hard masks are silicon nitride films orsilicon carbide films.
 18. A method for manufacturing a semiconductordevice according to claim 17, wherein said method comprises a processfor forming an etching stopper on said first interconnect prior to saidfirst process, said first methylsiloxane type film is formed on saidetching stopper in said first process, and a hole is formed in layeredfilms of said etching stopper, said first methylsiloxane type film andsaid first insulating film.
 19. A method for manufacturing asemiconductor device according to claim 18, wherein said etching stopperis a silicon nitride film or a silicon carbide film.
 20. A method formanufacturing a semiconductor film according to claim 19, wherein saidsecond hard mask is also removed in said ninth process.
 21. A system formanufacturing a semiconductor device according to claim 17, wherein saidconductor film is layered films of a barrier metal film and a copperfilm.
 22. A method for manufacturing a semiconductor device according toclaim 21, wherein said barrier metal film is a titanium nitride film ora tantalum nitride film.
 23. A method for manufacturing a semiconductordevice according to claim 17, wherein said conductor film in said holeis a via, and said conductor film in said trench is a second levelinterconnect.
 24. A method for manufacturing a semiconductor device,comprising: a first process for forming a first methylsiloxane type filmon or over a first interconnect; a second process for forming a firstinsulating film different from the methylsiloxane type film on saidfirst methylsiloxane type film; a third process for forming a first hardmask on said first insulating film; a fourth process for forming asecond methylsiloxane type film on said first hard mask; a fifth processfor forming a second insulating film different from the methylsiloxanetype film on said second methylsiloxane type film; a sixth process forforming a second hard mask on said second insulating film; a seventhprocess for transferring a trench pattern to said second hard mask usinga first resist as mask, and removing said first resist; an eighthprocess for transferring a hole pattern having in-plane overlapping withsaid trench pattern to layered films comprising said first hard mask,said second methylsiloxane type film, and said second insulating filmusing a second resist as mask, and removing said second resist bylow-pressure oxygen plasma treatment; a ninth process for forming atrench in layered films comprising said second methylsiloxane type filmand said second insulating film using said first and said second hardmasks as masks, and forming a hole in layered films of said firstmethylsiloxane type film and said first insulating film, and exposing apart of said first interconnect; and a tenth process for forming aconductor film electrically connected with the first interconnect insidesaid trench and said hole formed in said ninth process.
 25. A method formanufacturing a semiconductor device according to claim 24, wherein saidfirst and said second insulating films have etching rate of ⅓ or less ofthat of the first and said second hard masks.
 26. A method formanufacturing a semiconductor device according to claim 25, wherein saidfirst and said second insulating films are silicon oxide films.
 27. Amethod for manufacturing a semiconductor device according to claim 26,wherein said first and said second methylsiloxane type films are organicSOG films.
 28. A semiconductor device according to claim 27, whereinsaid first and said second hard masks are silicon nitride films orsilicon carbide films.
 29. A method for manufacturing a semiconductordevice according to claim 28, wherein said method comprises a processfor forming an etching stopper on said first interconnect prior to saidfirst process, said first methylsiloxane type film is formed on saidetching stopper in said first process, and a hole is formed in layeredfilms of said etching stopper, said first methylsiloxane type film andsaid first insulating film in the ninth process.
 30. A method formanufacturing a semiconductor device according to claim 29, wherein saidetching stopper is a silicon nitride film or a silicon carbide film. 31.A method for manufacturing a semiconductor device according to claim 30,wherein said second hard mask is also removed in said ninth process. 32.A system for manufacturing a semiconductor device according to claim 28,wherein said conductor film is layered films of a barrier metal film anda copper film.
 33. A method for manufacturing a semiconductor deviceaccording to claim 32, wherein said barrier metal film is a titaniumnitride film or a tantalum nitride film.
 34. A method for manufacturinga semiconductor device according to claim 28, wherein said conductorfilm in said hole is a via, and said conductor film in said trench is asecond interconnect.
 35. A semiconductor device, comprising: aninter-level dielectric and an interconnect formed by dual damasceneprocess in said inter-level dielectric; and said inter-layer dielectricfilm comprises at least a fist methylsiloxane type film, a firstinsulating film, a hard mask, a second methylsiloxane type film, and asecond insulating film laminated on each other in the order from thesemiconductor substrate side.
 36. A semiconductor device according toclaim 35, wherein said first and said second insulating films aresilicon oxide films.
 37. A semiconductor device according to claim 36,wherein said methylsiloxane type film is an organic SOG film.
 38. Asemiconductor device according to claim 37, wherein said hard mask is asilicon nitride film or a silicon carbide film.
 39. A semiconductordevice according to claim 38, wherein said inter-layer dielectriccomprises an etching stopper at a position closer to said semiconductorsubstrate than the first methylsiloxane type film.
 40. A semiconductordevice according to claim 39, wherein said etching stopper is a siliconnitride film or a silicon carbide film.
 41. A semiconductor deviceaccording to claim 35, wherein said interconnect is designed in suchmanner that an electrical connection perpendicular with respect to saidsemiconductor substrate is formed in layered films of said firstmethylsiloxane film and said first insulating film, and an electricalconnection in horizontal direction with respect to said semiconductorsubstrate is formed in layered films of said second methylsiloxane typefilm and said second insulating film.
 42. A method for manufacturing asemiconductor device, comprising: a first process for forming an etchingstopper on a first conductor film; a second process for forming amethylsiloxane type film on or over said etching stopper; a thirdprocess for forming an insulating film different from the methylsiloxanetype film on the methylsiloxane type film; a fourth process for forminga hard mask on the insulating film; a fifth process for transferring apattern to the hard mask using a photoresist mask, and removing thephotoresist mask; a sixth process for partially removing layered filmsof said methylsiloxane type film and said insulating film using the hardmask as a mask; a seventh process for partially removing said etchingstopper for exposing a part of said first conductor film and forremoving said hard mask; and an eighth process for forming a secondconductor film electrically connected with said first conductor film ona recess of said layered films formed in said sixth process.
 43. Amethod for manufacturing a semiconductor device according to claim 42,wherein an etching rate of said insulating film is ⅓ or less of anetching rate of the hard mask.
 44. A method for manufacturing asemiconductor device according to claim 43, wherein said insulating filmis a silicon oxide film.
 45. A method for manufacturing a semiconductordevice according to claim 42, wherein said methylsiloxane type film isan organic SOG film.
 46. A method for manufacturing a semiconductordevice according to claim 42, wherein said hard mask is a siliconnitride film or a silicon carbide film.
 47. A method for manufacturing asemiconductor device according to claim 42, wherein said etching stopperis a silicon nitride film or a silicon carbide film.
 48. A method formanufacturing a semiconductor device according to claim 42, wherein saidfirst and said second conductor films are layered films of a barriermetal film and a copper film.
 49. A method for manufacturing asemiconductor device according to claim 48, wherein said barrier metalfilm is a titanium nitride film or a tantalum nitride film.
 50. A methodfor manufacturing a semiconductor device according to claim 42, whereinsaid first conductor film forms a via for interconnection, and saidsecond conductor film forms a wiring for interconnection.
 51. A methodfor manufacturing a semiconductor device according to claim 42, whereinsaid first conductor film forms a wiring for interconnection, and saidsecond conductor film forms a via for interconnection.
 52. A method formanufacturing a semiconductor device, comprising: a first process forforming an etching stopper on a first conductor film; a second processfor forming a first methylsiloxane type film on or over said etchingstopper; a third process for forming a first insulating film differentfrom the methylsiloxane type film on said first methylsiloxane typefilm; a fourth process for forming a first hard mask on said firstinsulating film; a fifth process for transferring a hole pattern to saidfirst hard mask using a first photoresist mask, and removing said firstphotoresist mask; a sixth process for forming a second methylsiloxanetype film on said first hard mask; a seventh process for forming asecond insulating film different from the methylsiloxane type film onsaid second methylsiloxane type film; an eighth process for forming asecond hard mask on said second insulating film; a ninth process fortransferring a trench pattern having in-plane overlapping with said holepattern to said second hard mask using a second photoresist mask, andremoving said second photoresist mask; a tenth process for forming atrench in layered films of said second methylsiloxane type film and saidsecond insulating film using said first and said second hard masks asmasks, and forming a hole in layered films of said first methylsiloxanetype film and said first insulating film; an eleventh process forpartially removing said etching stopper for exposing a part of saidfirst conductor film and for removing said second hard mask; and atwelfth process for forming a second conductor film electricallyconnected with said first conductor film inside said trench and saidhole formed in said tenth and eleventh processes.
 53. A method formanufacturing a semiconductor device according to claim 52, wherein saidfirst and said second insulating films have etching rate of ⅓ or less ofthose of said first and second hard masks.
 54. A method formanufacturing a semiconductor device according to claim 52, wherein saidfirst and said second insulating films are silicon oxide films.
 55. Amethod for manufacturing a semiconductor device according to claim 52,wherein said first and second methylsiloxane type films are organic SOGfilms.
 56. A method for manufacturing a semiconductor device accordingto claim 52, wherein each of said first and second hard masks is asilicon nitride film or silicon carbide film.
 57. A method formanufacturing a semiconductor device according to claim 52, wherein saidetching stopper is a silicon nitride film or a silicon carbide film. 58.A method for manufacturing a semiconductor device according to claim 52,wherein said first and second conductor films are layered films of abarrier metal film and a copper film.
 59. A method for manufacturing asemiconductor device according to claim 58, wherein said barrier metalfilm is a titanium nitride film or a tantalum nitride film.
 60. A methodfor manufacturing a semiconductor device according to claim 52, whereinsaid second conductor film in said hole forms a via for interconnection,and said second conductor film in said trench forms a second levelwiring for interconnection.
 61. A method for manufacturing asemiconductor device, comprising: forming an etching stopper on a firstconductor film; forming a methylsiloxane type film on or over saidetching stopper; forming an insulating film different from themethylsiloxane type film on the methylsiloxane type film; forming a hardmask on the insulating film; transferring a pattern to the hard maskusing a photoresist mask, and removing the photoresist mask; partiallyremoving layered films of said methylsiloxane type film and saidinsulating film using the hard mask as a mask; partially removing saidetching stopper, so as to expose a part of said first conductor film,and removing said hard mask; and forming a second conductor filmelectrically connected with said first conductor film on a recess ofsaid layered films formed by said partial removing of said layeredfilms.
 62. A method for manufacturing a semiconductor device accordingto claim 61, wherein an etching rate of said insulating film is ⅓ orless of an etching rate of the hard mask.
 63. A method for manufacturinga semiconductor device according to claim 62, wherein said insulatingfilm is a silicon oxide film.
 64. A method for manufacturing asemiconductor device according to claim 61, wherein said methylsiloxanetype film is an organic SOG film.
 65. A method for manufacturing asemiconductor device according to claim 61, wherein said hard mask is asilicon nitride film or a silicon carbide film.
 66. A method formanufacturing a semiconductor device according to claim 61, wherein saidetching stopper is a silicon nitride film or a silicon carbide film. 67.A method for manufacturing a semiconductor device according to claim 61,wherein said first and said second conductor films are layered films ofa barrier metal film and a copper film.
 68. A method for manufacturing asemiconductor device according to claim 67, wherein said barrier metalfilm is a titanium nitride film or a tantalum nitride film.
 69. A methodfor manufacturing a semiconductor device according to claim 61, whereinsaid first conductor film forms a via for interconnection, and saidsecond conductor film forms a wiring for interconnection.
 70. A methodfor manufacturing a semiconductor device according to claim 61, whereinsaid first conductor film forms a wiring for interconnection, and saidsecond conductor film forms a via for interconnection.
 71. A method formanufacturing a semiconductor device, comprising: forming an etchingstopper on a first conductor film; forming a first methylsiloxane typefilm on or over said etching stopper; forming a first insulating filmdifferent from the methylsiloxane type film on said first methylsiloxanetype film; forming a first hard mask on said first insulating film;transferring a hole pattern to said first hard mask using a firstphotoresist mask, and removing said first photoresist mask; forming asecond methylsiloxane type film on said first hard mask; forming asecond insulating film different from the methylsiloxane type film onsaid second methylsiloxane type film; forming a second hard mask on saidsecond insulating film; transferring a trench pattern having in-planeoverlapping with said hole pattern to said second hard mask using asecond photoresist mask, and removing said second photoresist mask;forming a trench in layered films of said second methylsiloxane typefilm and said second insulating film using said first and said secondhard masks as masks, and forming a hole in layered films of said firstmethylsiloxane type film and said first insulating film; partiallyremoving said etching stopper, so as to expose a part of said firstconductor film, and removing said second hard mask; and forming a secondconductor film electrically connected with said first conductor filminside said trench and said hole.
 72. A method for manufacturing asemiconductor device according to claim 71, wherein said first and saidsecond insulating films have etching rate of ⅓ or less of those of saidfirst and second hard masks.
 73. A method for manufacturing asemiconductor device according to claim 71, wherein said first and saidsecond insulating films are silicon oxide films.
 74. A method formanufacturing a semiconductor device according to claim 71, wherein saidfirst and second methylsiloxane type films are organic SOG films.
 75. Amethod for manufacturing a semiconductor device according to claim 71,wherein each of said first and second hard masks is a silicon nitridefilm or silicon carbide film.
 76. A method for manufacturing asemiconductor device according to claim 71, wherein said etching stopperis a silicon nitride film or a silicon carbide film.
 77. A method formanufacturing a semiconductor device according to claim 71, wherein saidfirst and second conductor films are layered films of a barrier metalfilm and a copper film.
 78. A method for manufacturing a semiconductordevice according to claim 77, wherein said barrier metal film is atitanium nitride film or a tantalum nitride film.
 79. A method formanufacturing a semiconductor device according to claim 71, wherein saidsecond conductor film in said hole forms a via for interconnection, andsaid second conductor film in said trench forms a second level wiringfor interconnection.